This invention relates to a semiconductor memory device and to a technique which will be particularly effective when utilized for dynamic RAMs (Random Access Memories) having a plurality of memory arrays, although the invention is not limited to this.
Dynamic RAMs having a plurality of memory arrays are known. The dynamic RAM includes row address decoders, column address decoders, sense amplifiers, main amplifiers, and the like, that are disposed so as to correspond to the memory arrays.
Such a dynamic RAM having a plurality of memory arrays is described, for example, in "Hitachi IC Memory Data Book", September, 1985, pp. 263-268, published by Hitachi, Ltd.